module Count(
  input        clock,
  input        reset,
  input        io_en,
  output       io_valid,
  output [7:0] io_out
);

  reg [7:0] a;
  wire  wrap_wrap = a == 8'he8;
  wire [7:0] _wrap_value_T_1 = a + 8'h1;

  assign io_valid = io_en & wrap_wrap;
  assign io_out = a;

  always @(posedge clock) begin
    if (reset) begin
      a <= 8'h0;
    end else if (io_en) begin
      if (wrap_wrap) begin
        a <= 8'h0;
      end else begin
        a <= _wrap_value_T_1;
      end
    end
  end

endmodule
